A microelectronic device such as a Field-Programmable Gate Array (FPGA) includes a large number of elements, typically logic gates, which can be individually configured or programmed to provide a desired logical functionality. Input and output pins enable external connection of the elements. Setup and hold times relate to the timing relationship between data and clock pulses applied to an element which is configured as a flip-flop or any other bistable element. Flip-flops and similarly configured elements are typically used as memory and register cells.
The setup time is the minimum length of time that a data signal must be available and stable at an input of a flip-flop before a leading edge of clock pulse is applied. If the clock pulse is applied too soon after the data signal, the setup time will be violated (less than the minimum length of time) and the flip-flop will not predictably produce the desired output signal, i.e. a signal having the same logic state as the data input signal.
The hold time is similar to the setup time, and is the minimum length of time that the data must be available and stable after the leading edge of the clock pulse. If the hold time is violated, the flip-flop will not accurately register the new data. The setup and hold times are related as will be described in detail below.
The setup and hold times of FPGAs and other microelectronic devices must be accurately tested to maintain quality control and predict device performance. This testing is conventionally performed manually using a procedure as illustrated in FIG. 1.
As shown in the drawing, a testing system 10 includes a 2-channel pulse generator 12 which generates data pulses DATA and clock pulses CLOCK, and a 3-channel oscilloscope 14 which receives the DATA, CLOCK and output pulses OUTPUT from a microelectronic device 16 under test at its three input channels. The device 16 is inserted in an appropriate test socket (not shown), and supplied with appropriate operating voltages by a power supply 18. A personal computer 20 is further illustrated for storing the test results.
The testing is performed by a human operator 22 who manually manipulates the illustrated components of the system 10. The procedure for measuring the setup time is shown in FIGS. 2 to 4. The test is performed for each element of the device 16, during which an element 24 being tested is preferably configured as a D-type flip-flop having a data input D, a clock input C and a positive logic output Q.
As illustrated in FIGS. 1 and 2, the pulse generator 12 generates first pulses, in this case the clock pulses CLOCK, and second pulses, in this case the data pulses DATA, which appear on the oscilloscope 14. If the setup time of the element 24 is not violated, or if the leading edges of the first or CLOCK pulses are applied more than a minimum length (the setup time) after the leading edges of the second or DATA pulses, the element 24 will produce the OUTPUT pulses having leading edges which appear shortly after the leading edges of the CLOCK pulses. If the setup time is violated, the OUTPUT pulses will not be predictable.
The CLOCK pulses are applied to the element 24 without any time delay, or with a predetermined fixed time delay. The leading edges of the CLOCK pulses will always appear on the oscilloscope 14 at a relative time T0. However, the pulse generator 12 is able to generate the DATA pulses with a variable delay relative to the CLOCK pulses such that DATA pulses appear to move toward (shift rightwardly) or away (shift leftwardly) from the CLOCK pulses.
Increasing the delay causes the DATA pulses to move rightwardly toward the CLOCK pulses and vice-versa. Of course, an equivalent result can be obtained by generating the DATA pulses with a fixed delay and generating the CLOCK pulses with a variable delay, or suitably delaying both the DATA and CLOCK pulses.
The operator 22 controls the pulse generator 12 such that the DATA pulses are initially generated so their leading edges appear on the oscilloscope 14 at a relative time T1. The difference between the relative times T0 and T1 is designated as a first value D1 of delay of the DATA pulses relative to the CLOCK pulses. The delay D1 is selected to be sufficiently larger than the setup time that the OUTPUT pulses will accurately appear.
Then, referring to FIGS. 1 and 3, the operator 22 increases the delay of the DATA pulses as indicated by an arrow 26 to a relative time T2 at which the relative delay has a third value D3. At this transition point, the OUTPUT pulses disappear as indicated by the broken line.
Referring to FIGS. 1 and 4, the operator 22 then decreases the delay of the DATA pulses as indicated by an arrow 28 until a relative time T3 is reached at which the relative delay has a value of D2. At this transition point, the OUTPUT pulses reappear as indicated in solid line.
The operator 22 then uses the oscilloscope 14 to manually measure the delay D2 (the difference between the relative times T0 and T3), which is the minimum length of time or the setup time as described above, and stores an identification number for the element 24 and the corresponding setup time in the computer 20. Note that the horizontal time scale of the oscilloscope is typically calibrated in nanoseconds (ns) as illustrated in FIGS. 2 to 4 to enable visual readings of the relative times T0 and T3 and calculation of the difference therebetween based on the visual readings.
As described above, the delay of the DATA pulses is changed so that the OUTPUT pulses first disappear as viewed in FIG. 3 and then reappear as viewed in FIG. 4. This is done because there is a metastable area in the relative delay time in which the setup time is violated for some pulses and not for others.
However, it is possible to practice this method by performing only the steps of FIGS. 2 and 3, and designating the delay D3 as the setup time. It is also possible to practice the method by starting with a delay of the DATA pulses relative to the CLOCK pulses which is sufficiently small or negative to ensure that the OUTPUT pulses do not appear, and then decreasing the delay of the DATA pulses until the pulses appear. These alternative methods will produce results which may be satisfactory for some applications, but will not be as accurate as the method illustrated in FIGS. 2 to 4.
The conventional method described above, although capable of measuring setup and hold times with a useful degree of accuracy, suffers from major drawback in that it is performed manually by a human operator. This manual operation is very slow compared to a computer-automated operation, and is also limited in accuracy in that the operator must subjectively judge the delay using a relatively crude time scale on the oscilloscope. This manual operation is further undesirable in that the accuracy can be adversely affected by the operator's eyesight, emotional level, fatigue, stress level and other factors.